Method, apparatus, and system for targeted healing of write fails through bias temperature instability

ABSTRACT

Method, apparatus, and system for improving semiconductor device writeability at row/bit level through bias temperature instability. Such a device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. By virtue of BTI, application of the first array supply voltage may lead to improved writeability of one or more cells of the device.

BACKGROUND OF THE INVENTION

Field of the Invention

Generally, the present disclosure relates to the manufacture and use of sophisticated semiconductor devices, and, more specifically, to various methods, structures, and systems for improving the yield and/or reliability of semiconductor devices by exploitation of bias temperature instability (BTI).

Description of the Related Art

The manufacture of semiconductor devices requires a number of discrete process steps to create a packaged semiconductor device from raw semiconductor material. The various processes, from the initial growth of the semiconductor material, the slicing of the semiconductor crystal into individual wafers, the fabrication stages (etching, doping, ion implanting, or the like), to the packaging and final testing of the completed device, are so different from one another and specialized that the processes may be performed in different manufacturing locations that contain different control schemes.

Generally, a set of processing steps is performed on a group of semiconductor wafers, sometimes referred to as a lot, using semiconductor-manufacturing tools, such as exposure tool or a stepper. As an example, an etch process may be performed on the semiconductor wafers to shape objects on the semiconductor wafer, such as polysilicon lines, each of which may function as a gate electrode for a transistor. As another example, a plurality of metal lines, e.g., aluminum or copper, may be formed that serve as conductive lines that connect one conductive region on the semiconductor wafer to another. In this manner, integrated circuit chips may be fabricated.

Bias temperature instability (BTI) remains as one of the key reliability concerns in advanced complementary metal-oxide-semiconductor (CMOS) nodes, such as those used in static random access memory (SRAM). Generally, BTI arises when a voltage is applied to one or more transistors or other elements of a device incorporating CMOS technologies, i.e., during normal device operation. Over time, BTI tends to weaken the drive strength of the transistor. Of further concern in multi-element devices, such as, for example, six-transistor (6T) SRAMs, is that unequal extents of BTI between different elements may lead to imbalances between writeability and read-stability (one cause of which is BTI shifts) that reduce yield of the circuit element more than would be expected from simply considering each BTI-undergoing element in isolation.

Field failures due to stress induced device shifts attributable to the BTI mechanism continue to plague very-large-scale integration (VLSI) CMOS technologies. Over product life time the Vmin is known to increase in large SRAM arrays due to negative bias temperature instability (NBTI) and more recently positive bias temperature instability (PBTI) combined with NBTI. SRAM arrays are particularly vulnerable due to the increased number of bits with each generation and use of minimum transistor size for maximum bit density.

The random nature of the BTI mechanism leaves large arrays vulnerable to BTI induced failures over the life time of the product. Therefore, BTI induced voltage sensitive failures in advanced VLSI SRAM arrays are expected to remain one of the key technology reliability concerns for the foreseeable future.

The industry has adopted voltage-guard-bands as the principle means to compensate for expected end of life BTI shifts. Though accepted, voltage-guard-bands are costly with limitations in effectiveness.

Therefore, it would be desirable to have solutions to the problem of BTI shifts that are relatively inexpensive, readily fabricated, and effective.

The present disclosure may address and/or at least reduce one or more of the problems identified above regarding the prior art and/or provide one or more of the desirable features listed above.

SUMMARY OF THE INVENTION

The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is discussed later.

Generally, the present disclosure is directed to various methods, apparatus, and systems, such as a semiconductor device comprising a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage.

The present disclosure is also directed to methods of improving the yield and/or reliability of semiconductor devices by use of bias temperature instability (BTI). One such method comprises identifying each cell suffering a write 0 failure in an array comprising a plurality of cells, wherein each of the cells comprises a pass gate and a latch; identifying each cell suffering a write 1 failure in the array; applying a first array supply voltage to the latch of each cell in a first subset of the cells and a write 1 to the pass gate of each cell in the first subset for a first duration, wherein the first subset of cells comprises all cells suffering a write 0 failure and the first array supply voltage is greater than an operational array supply voltage of the cell; and applying a second array supply voltage to the latch of each cell in a second subset of the cells and a write 0 to the pass gate of each cell in the second subset for a second duration, wherein the second subset of cells comprises all cells suffering a write 1 failure and the second array supply voltage is greater than an operational array supply voltage of the cell.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosure may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIG. 1 illustrates a stylized depiction of a semiconductor device in accordance with embodiments herein;

FIG. 2 illustrates a stylized depiction of a six-transistor (6T) static random access memory (SRAM) cell in accordance with embodiments herein;

FIG. 3 illustrates the yield, the writeability sigma, and the read-stability sigma as a function of SNM for a typical 6T SRAM cell in accordance with embodiments herein;

FIG. 4 illustrates a stylized depiction of a 6T SRAM cell in accordance with embodiments herein;

FIG. 5 illustrates a semiconductor device manufacturing system for manufacturing a device in accordance with embodiments herein;

FIG. 6 illustrates a flowchart of a method in accordance with embodiments herein;

FIG. 7 presents a timing diagram usable in a step of the method shown in FIG. 6 in accordance with embodiments herein; and

FIG. 8 illustrates a flowchart of a step of the method shown in FIG. 6 in accordance with embodiments herein.

While the subject matter disclosed herein is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific embodiments is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

RELATED APPLICATIONS

The following applications, filed the same date as the instant application, are hereby incorporated by reference herein. Ser. No. ______, entitled “Method, Apparatus, And System For Global Healing of Stability-Limited Die Through Bias Temperature Instability,” Attorney Docket No. HU259C/4014.260400; Ser. No. ______, entitled “Method, Apparatus, And System For Targeted Healing Of Stability Failures Through Bias Temperature Instability,” Attorney Docket No. HU259A/4014.260500; and Ser. No. ______, entitled “Method, Apparatus, And System For Global Healing Of Write-Limited Die Through Bias Temperature Instability,” Attorney Docket No. HU259D/4014.260600.

DETAILED DESCRIPTION

Various illustrative embodiments of the invention are described below. In the interest of clarity, not all features of an actual implementation are described in this specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art having the benefit of this disclosure.

The present subject matter will now be described with reference to the attached figures. Various structures, systems and devices are schematically depicted in the drawings for purposes of explanation only and so as to not obscure the present disclosure with details that are well known to those skilled in the art. Nevertheless, the attached drawings are included to describe and explain illustrative examples of the present disclosure. The words and phrases used herein should be understood and interpreted to have a meaning consistent with the understanding of those words and phrases by those skilled in the relevant art. No special definition of a term or phrase, i.e., a definition that is different from the ordinary and customary meaning as understood by those skilled in the art, is intended to be implied by consistent usage of the term or phrase herein. To the extent that a term or phrase is intended to have a special meaning, i.e., a meaning other than that understood by skilled artisans, such a special definition will be expressly set forth in the specification in a definitional manner that directly and unequivocally provides the special definition for the term or phrase.

Embodiments herein provide for improved yield and/or reliability of semiconductor devices by use of bias temperature instability (BTI).

Turning now to FIG. 1, we present a stylized depiction of a semiconductor device 100 in accordance with embodiments herein. As shown, the semiconductor device 100 comprises an array 105. The array 105 comprises a plurality of cells 110 a-1 through 110 n-2 (collectively “110”). Each of the cells 110 comprises at least one pass gate (PG) 120 and a latch 130. The depicted embodiment shows each of the latches 130 comprising one supply voltage line input. It should be noted in other embodiments, the latches 130 may comprise two supply voltage line inputs, which may be used for cells 110 of a six-transistor static random access memory (6T SRAM), wherein two of a latch's four transistors (e.g., PUL 132L and PDL 134L of latch 130 in FIG. 2) are electrically connected to one VCS input and the other two of the latch's four transistors (e.g., PUR 132R and PDR 134R of latch 130 in FIG. 2) are electrically connected to the other VCS input.

The semiconductor device 100 also comprises a plurality of word lines (WL) a, b, . . . n. Each word line controls access to a first number of cells 110. In the depicted embodiment, word line a controls access to cell 110 a-1 and cell 120 a-2. As can be seen, the reference character of each word line (e.g., a, b, . . . n) indicates the word line controls access to the various cells 110, which have the same suffixed letter as the word line a, b, . . . n and an incremented suffixed numeral −1 or −2.

The semiconductor device 100 also comprises appropriate, known logic (not shown) by which each cell 110 of each word line a, b, . . . n can receive a write 0 or write 1 for any desired proportion of time. For example, in various embodiments discussed below, the semiconductor device 100 may comprise logic whereby none, some, or all cells 110 can receive a write 0 for 50% of a time period and a write 1 for 50% of the time period.

Although FIG. 1 depicts one word line, e.g., word line a, controlling access to two cells 110 a-1 and 110 a-2, the person of ordinary skill in the art will appreciate that more than two cells 110 may have access thereto controlled by a single word line a, b, . . . n. For example, in embodiments wherein the cell 110 is an SRAM cell, from two to sixty-four cells 110, for example, two, four, eight, sixteen, thirty-two, or sixty-four cells 110, or more generally, 2^(x) cells 110, wherein x is a counting number, may have access thereto controlled by a single word line a, b, . . . n. In one embodiment, eight cells 110 have access thereto controlled by a single word line a, b, . . . n.

Similarly, although FIG. 1 depicts three word lines a, b, and n, the person of ordinary skill in the art will appreciate that any number of word lines may be included in the array 105. For example, in embodiments wherein the array 105 comprises SRAM cells, such an array may comprise eleven word lines. Greater or lesser numbers of word lines may be present, depending on the desired use of the array and considerations relating to manufacturing complexity, among other considerations that will be apparent to the person of ordinary skill in the art.

Turning to FIG. 2, an embodiment wherein the cell 110 is a six-transistor (6T) SRAM cell is depicted. As shown, word line a controls access to left pass gate (PGL) 120L and right pass gate (PGR) 120R. The other four transistors of the 6T SRAM cell make up the latch 130. The four transistors of the latch 130 are a pull up left (PUL) transistor 132L, a pull down left (PDL) transistor 134L, a pull up right (PUR) transistor 132R, and a pull down right (PDR) transistor 134R. The operation of a 6T SRAM cell to store a bit is well known and will not be discussed in detail at this time.

Returning to FIG. 1, the semiconductor device 100 comprises an array VCS driver 160 electrically connected to each word line's VCS 150 a, 150 b, . . . 150 n. The array VCS driver 160 provides electrical current required for each word line a, b, . . . n to read a 0 or 1 bit from each latch 130 controlled by that word line.

The voltage provided by array VCS driver 160 to each VCS 150 a, 150 b, . . . 150 n is controlled by control line 170. The control line 170 may be configured to provide an operational array supply voltage (Vnom, supplied by line 180) or a first array supply voltage (VSTR, supplied by line 190) through the array VCS driver 160. In some embodiments, the control line 170 may be a built-in self-heal for writes (BISHW) line, by which is meant a line that controls whether the semiconductor device 100 implements a self-healing process for correcting write errors in one or more cells 110 of array 105.

In the depicted embodiment, if control line 170 is deasserted (e.g., if BISHW=0), then the gate of operational array supply voltage transistor 182 is open and current flows from Vnom 180 through operational array supply voltage transistor 182 to array VCS driver 160. Inverter 183 passes an assertion to first array supply voltage transistor 184, which closes the gate of first array supply voltage transistor 184, thereby preventing current flow from VSTR 190 to array VCS driver 160. Thus, if control line 170 is deasserted, each latch 130 a-1, 130 a-2, 130 b-1, . . . 130 n-2 of array 105 receives the operational array supply voltage.

On the other hand, if control line 170 is asserted (e.g., if BISHW=1), then the gate of operational array supply voltage transistor 182 is closed, and current flow from Vnom 160 is prevented. Inverter 183 passes a deassertion to first and/or second array supply voltage transistor 184, which opens the gate of first and/or second array supply voltage transistor 184, thereby allowing current flow from VSTR 190 to array VCS driver 160. Thus, if control line 170 is asserted, each latch 130 a-1, 130 a-2, 130 b-1, . . . 130 n-2 of array 105 receives the first and/or second array supply voltage.

Although a particular arrangement of transistors 182 and 184 and inverters 183 is depicted in FIG. 1, the person of ordinary skill in the art, having the benefit of the present disclosure, will be able to construct alternative arrangements of logic gates whereby a control line may provide an operational array supply voltage or a first and/or second array supply voltage to each word line of a plurality of cells in an array through an array VCS driver.

The present disclosure is not limited to any particular value of the operational array supply voltage (Vnom 180) or the first and/or second array supply voltage (VSTR 190). In one embodiment, the operational array supply voltage may be about 1.0 V and the first and/or second array supply voltage may be from about 1.1V to about 1.6V. In relative terms, in one embodiment, the first and/or second array supply voltage may be from about 1.1 times the operational array supply voltage to about 1.8 times the operational array supply voltage.

Example

Although the next several paragraphs will discuss an example of healing of bits with failing stability, the person of ordinary skill in the art, having the benefit of the present disclosure, will understand the principles embodied in this example are applicable to the healing of bits with failing writeability.

Though not to be bound by theory, turning to FIGS. 3-6, we review how to significantly reduce the vulnerability to BTI fails. By controlled selective bias of targeted failing bits, fails or shifts in Vmin can be rectified. This is accomplished with existing array design architectures using only the existing built in terminals (BL, BL, WL, VCS and VSS).

The concepts required for “healing” of failed or failing bits in large SRAM arrays on advanced CMOS nodes are discussed and demonstrated with both (20 nm and 14 nm) hardware. As scaling continues below 20 nm, greater than 500 Mb of SRAM on a die is not uncommon. The migration to FinFET devices and the lithographic challenges in printing and controlling the dimensions has become increasingly difficult. The 6T SRAM bit cell is a common feature of contemporary semiconductor devices and SRAM bit cell area is a benchmark of technology competitiveness in today's VLSI microelectronics industry.

A significant source of variation in nanoscale CMOS technologies is associated with random dopant fluctuations (RDF), which follow a 1/√WL relationship. Although high-k/metal gate technologies have provided some relief, aggressive design rule and device scaling has led to an increase in device variation in both SRAM and logic devices. Because it is common for the SRAM devices to be near or below minimum logic design rules, the RDF mismatch phenomenon is exacerbated. Additionally, pushed design spacing rules used in the dense SRAM cell can lead to added sources of variation that is not observed in circuits designed with the standard logic design rules. These factors among others coupled with additional variation and within-cell asymmetric shifts associated with BTI result in heightened vulnerability for the SRAM.

Positive BTI (PBTI) and negative BTI (NBTI) can be expressed as follows.

${{PBTI}\; \Delta \; {{Vt}\left( {{yr},{Vg},T} \right)}}:={A \cdot {mV} \cdot {\exp \left\lbrack \frac{Ea}{k\; {2 \cdot \left( {{273 \cdot K} + T} \right)}} \right\rbrack} \cdot \left( \frac{Vg}{tinv} \right)^{m} \cdot {{tt}\left( {{yr} \cdot {df}} \right)}^{n} \cdot W^{\beta} \cdot L^{\alpha}}$ ${{NBTI}\; \Delta \; {{Vt}\left( {{yr},{Vg},T} \right)}}:={{Ap} \cdot {mV} \cdot {\exp \left\lbrack \frac{Eap}{k\; {2 \cdot \left( {{273 \cdot K} + T} \right)}} \right\rbrack} \cdot \left( \frac{Vg}{tinvp} \right)^{mp} \cdot {{tt}\left( {{yr} \cdot {df}} \right)}^{np} \cdot W^{\beta \; p} \cdot L^{\alpha \; p}}$

The 6T SRAM cell design and functionality relies on a balance between maintaining the ability to write, and ability to maintain state. This intrinsic tradeoff is represented in FIG. 3 which illustrates with yield (solid line) and sigma (dashed lines) the balance between stability and write margin. The maximum yield is obtained when these are balanced. Maintaining this balance fundamentally relies on device targeting and maintaining a tight control of both local and global variation for the transistors. Although RDF remains a large source of variation (even with FinFET devices that rely on halo and channel doping to target the threshold), over the lifetime of the product, the increased variation attributable to BTI is also a factor.

FIG. 4 illustrates the devices within cell 110 being stressed when the array is powered on in the situation where Q is low and Q is high. It is clear that the PUR 132R and PDL 134L devices of latch 130 are continuously experiencing bias consistent with the BTI stress condition. Specifically, in this situation, PDL 134L experiences PBTI and PUR 132R experiences NBTI. The state of the bit governs which pair of PD/PU devices is receiving the BTI bias conditions. In the situation where Q is high and Q is low, PUL 132L and PDR 134R undergo BTI.

Over the product lifetime, the bits may be expected to switch, and thus the amount of time spent in one state (e.g., Q low and Q high) is only a fraction of the total lifetime. If the fraction is close to 50%, the mean net shift is on both pairs would be approximately the same, which may support the balance between writeability and read-stability. However, in actual practice, the fraction is rarely close to 50% for several reasons. The actual fraction of time any individual bit is holding a specific state can be a source of error in predicting the voltage-guard-band needed for a product. In practice, the fraction of SRAM bits storing a 0 state is typically somewhat higher by several percent compared to bits storing a 1 state. The result is a significant fraction of the bits in the array will see an uneven stress so that the PDL and PUR latch devices may see far more BTI stress than the PDR and PUL in the same bit.

To gain performance, it has become common industry practice to overdrive the voltage which exacerbates the BTI impact. This impacts the SRAM for each terminal (VCS/WL/NW and BL) unless specific voltage domains are included for the SRAM.

The voltage-guard-band is used throughout the VLSI CMOS industry to provide a buffer for expected Vmin shifts associated with the BTI mechanism. As discussed above, this approach is both costly and has limitations in its ability to capture rogue bit shifts. The typical guard band may be 50 mV or more depending on the anticipated device shifts over the product life. In addition to the BTI voltage-guard-band, it is common practice to add additional voltage-guard-bands to account for tester variability and other noise sources, such as IR drop and potentially random telegraph noise (RTN). The inclusion of voltage-guard-bands further complicates SRAM array fabrication, requiring further testing to ensure devices meet specifications. As a result of the guard-band approach, many potentially good die are discarded costing fabs millions in revenue each year.

By using an extended write or repeat write with elevated WL voltage the Vt of the PG device can be increased by the PBTI mechanism, by selectively raising the PG device Vt on the selected bits. Thereby, bits with failing stability may be healed.

In healing bits with failing stability, once a bit is deemed to have reduced stability by failing or by the fact that it is the bit limiting the Vmin of the array, it is crucial to know the state in which the bit is unstable. For example, if the bit is failing when storing a 0 on node Q, to improve the stability of this bit, the controlled biasing scheme, using the write circuitry and elevated WL bias would be used so that the PGL device 120L of cell 110 is subject to PBTI stress.

In the on state condition for the SRAM array 105, the latch devices 130 for the entire array 105 of SRAM bits 110 are continuously biased and subject to BTI induced shifts. This leads to a mean shift in the pull-up (PU) and pull-down (PD) devices over time which leads to reduced stability. The word line or (PG) devices are largely unimpacted due to the significantly reduced stress time. Because of this, over time in an HTOL or in the field, the latch 110 stability becomes weaker (relative to the PG 120).

The controlled bias write step could be exercised multiple times (word selections may be varied but would contain this bit) to reduce PBTI shifts in bits on the same word line. In practice, 5-15 mV positive shifts in Vtsat will be expected to sufficiently restore a bit. It is recognized that other PG devices 120 along the word line will also experience a shift. This can be minimized by writing multiple times and exchanging word (keeping the target bit constant). Alternatively, as was done in the experiments described herein, the other PG devices 120 on the same word line are allowed to be impacted, reducing read or write performance for a limited number of bits 110 on the selected word line. Even so, only a tiny fraction of bits 110 from the entire array 105 will experience a small net degrade in read and write performance.

Using the existing VLSI architecture for SRAM arrays 105, sufficient ports are available to apply the biases needed to achieve the desired stresses. Read and write operations along with addressable bit selection exist and may be exploited to heal bits via BTI.

While the read operation does not provide the desired BTI stress conditions, the addressable write condition is well suited to achieve the desired PBTI stress for the PG devices 120. As discussed earlier, during normal use conditions while the array 105 is powered, two devices of latch 130 are continuously subject to BTI stress. Over the course of an HTOL stress or product life, these devices of latch 130 become weaker due to BTI. With an elevated WL voltage and extended write time or multiple writes to the target bit, sufficient PG device 120 shifts can be obtained. The intentional positive shift in the PG 120 weakens the targeted PG device 120 so that it is matched with the devices of latch 130 in drive strength.

The voltages and times required to accomplish the recovery of Vmin are less than the typical dynamic voltage screen (DVS) [typically 1.6-1.8 times Vnom] and hence pose no significant threat to the integrity of the small fraction of devices experiencing the elevated voltage. By incorporating BIST to catch bits 110 that begin to show signs of weakness, the voltage and times required to restore the weakest bits 110 may be kept sufficiently low as to be non-consequential.

Regarding the healing of stability fails, using 20 nm hardware, by biasing at wafer level the WLs in a mini-SRAM-array 105 at an elevated voltage (1.4V), much as 3-4 mV of Vt shift was obtained with less than 5 seconds using the elevated WL voltage.

With the concepts and validation experiments have been laid out in the previous sections, demonstration using a 128 Mb functional SRAM is discussed. A 20 nm technology 128 Mb SRAM module, identified as failing 0.8V Vmin with a single cell fail (SCF) after an HTOL-like stress of 1.4 times Vnom for 168 hours, was selected. The fail was determined to be a stability or ‘read’ failure. Because it was a read 0 fail, a write 0 operation was applied for 1 second intervals. Initially the part was subjected to 10 read operations at 0.8V and found to fail 10 of 10 or 100% of the read operations. After 4 seconds of writing 0 with 1.4 times Vnom on the WL 150, the part was found to have 0 fails of 10 read passes at 0.8V in the 128 Mb array. The expected PG 120 Vt shift was approximately 10-15 mV which reduced the PG 120 strength sufficiently to be properly balanced with the latch 130 strength.

This example is to our knowledge the first working proof of concept demonstrating the concept working in a large functional SRAM array 105. This opens the door to in-situ recovery or healing of bits which fail in the field over the life of the product. Although this proof of concept is specific to the healing of bits with failing stability, the principles embodied in this proof of concept are applicable to the healing of bits with failing writeability.

In summary, by exploiting the BTI mechanism, a selected bias induced healing of failing bits in VLSI SRAM functional arrays 105 has been demonstrated in both 20 nm and 14 nm nodes. We demonstrated a methodology to recover specific bits which failed or shifted in Vmin during an HTOL stress. Use of applied biases and times, on the order of those used in dynamic voltage screening, was shown to be effective in large functional SRAM arrays 105 using terminals available in such arrays. By use of this technique, coupled with BIST or error detection and minimal circuit overhead, it is possible to recover or “heal” or prevent BTI stress induced Vmin failures in the field.

Moving on from the example, turning now to FIG. 5, a stylized depiction of a system 500 for fabricating a semiconductor device 100, in accordance with embodiments herein, is illustrated. The system 500 of FIG. 5 may comprise a semiconductor device manufacturing system 510 and a process controller 520. The semiconductor device manufacturing system 510 may manufacture semiconductor devices 100 based upon one or more instruction sets provided by the process controller 520. In one embodiment, the instruction set may comprise instructions to form a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; form a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; form an array VCS driver electrically connected to each VCS; and form a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage.

The system 500 is not limited to particular details of the cells, the first number of cells, the number of cells in the array, the number of word lines in the device, the logic gates and related structures required for the control line to provide an operational array supply voltage or a first and/or second array supply voltage to each cell of each word line through the array VCS driver. In one embodiment, each cell is a static random access memory (SRAM) cell, such as a six-transistor (6T) SRAM cell. In one embodiment, the first number of cells is eight.

The system 500 also comprises a test and repair controller 530. The test and repair controller 530 may be configured to identify each cell suffering a write 0 failure in an array comprising a plurality of cells, wherein each of the cells comprises a pass gate and a latch; identify each cell suffering a write 1 failure in the array; apply a first array supply voltage to the latch of each cell in a first subset of the cells and a write 1 to the pass gate of each cell in the first subset for a first duration, wherein the first subset of cells comprises all cells suffering a write 0 failure and the first array supply voltage is greater than an operational array supply voltage of the cell; and apply a second array supply voltage to the latch of each cell in a second subset of the cells and a write 0 to the pass gate of each cell in the second subset for a second duration, wherein the second subset of cells comprises all cells suffering a write 1 failure and the second array supply voltage is greater than an operational array supply voltage of the cell. In one embodiment, the first array supply voltage may be from about 1.1 times the operational array supply voltage to about 1.8 times the operational array supply voltage. Independently, the second array supply voltage may be from about 1.1 times the operational array supply voltage to about 1.8 times the operational array supply voltage. Independently, in one embodiment, the first duration may be from about 1 sec to about 8 sec and/or the second duration may be from about 1 sec to about 8 sec. The specific time may be selected based on the technology, the temperature, and voltage.

In one embodiment, the test and repair controller 530 may be further configured to apply a write 0 to the pass gate of each cell in a third subset of cells for 50% of a third duration, and a write 1 to the pass gate of each cell in the third subset for 50% of the third duration, wherein the third subset comprises all cells not identified as suffering a write 0 failure and not identified as suffering a write 1 failure. Doing so may reduce degradation of the stability of cells which do not require healing of write 0 and/or write 1 failures.

The test and repair controller 530 may be configured to test one or more semiconductor devices 100 at any desired stage in processing. The test and repair controller 530 may also be configured to bidirectionally communicate with the process controller 520 regarding various aspects of processing. For example, the process controller 520 may communicate with the test and repair controller 530 to establish the value of the first and second array supply voltages in either absolute terms or terms relative to the operational array supply voltage, the length of the first duration, the length of the second duration, and/or other parameters regarding the desired stability of the plurality of cells 110 in array 105 of semiconductor device 100. In the other direction, the test and repair controller 530 may communicate with the process controller 520 regarding test conditions and results, including number of write 0 failures, the number of write 1 failures, the value of the first and/or second array supply voltages in either absolute terms or terms relative to the operational array supply voltage, the length of the first duration, the length of the second duration, and/or other parameters regarding the desired writeability of the plurality of cells 110. The process controller 520 may make use of test condition and result data from the test and repair controller 530 in modifying one or more parameters of the instruction set provided to the semiconductor device manufacturing system 510, such that semiconductor devices 100 may be manufactured to have a greater likelihood of having a desired writeability of the plurality of cells.

The semiconductor device manufacturing system 510 may comprise various processing stations, such as etch process stations, photolithography process stations, CMP process stations, etc. One or more of the processing steps performed by the semiconductor device manufacturing system 510 may be controlled by the process controller 520. The process controller 520 may be a workstation computer, a desktop computer, a laptop computer, a tablet computer, or any other type of computing device comprising one or more software products that are capable of controlling processes, receiving process feedback, receiving test results data, performing learning cycle adjustments, performing process adjustments, etc.

The semiconductor device manufacturing system 510 may produce semiconductor devices 100 (e.g., integrated circuits) on a medium, such as silicon wafers. The semiconductor device manufacturing system 510 may provide processed semiconductor devices 100 on a transport mechanism 550, such as a conveyor system. In some embodiments, the conveyor system may be sophisticated clean room transport systems that are capable of transporting semiconductor wafers. In one embodiment, the semiconductor device manufacturing system 510 may comprise a plurality of processing steps, e.g., the 1^(st) process step, the 2^(nd) process step, etc.

In some embodiments, the items labeled “100” may represent individual wafers, and in other embodiments, the items 100 may represent a group of semiconductor wafers, e.g., a “lot” of semiconductor wafers. The semiconductor device 100 may comprise one or more of a transistor, a capacitor, a resistor, a memory cell, a processor, and/or the like. In one embodiment, the semiconductor device 100 comprises a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage.

The system 500 may be capable of manufacturing various products involving various technologies. For example, the system 500 may produce devices of CMOS technology, Flash technology, BiCMOS technology, power devices, memory devices (e.g., DRAM devices), NAND memory devices, and/or various other semiconductor technologies.

Turning to FIG. 6, a flowchart of a method 600 in accordance with embodiments herein is depicted. The method 600 may comprise identifying (at 610) cells suffering write 0 failures in an array 105 comprising a plurality of cells 110, wherein each of the cells 110 comprises a pass gate 120 and a latch 130.

The method 600 may also comprise identifying (at 620) cells suffering write 1 failures.

Thereafter, method 600 may comprise applying (at 630) a first array supply voltage to the latch 130 of each cell 110 in a first subset of the cells and a write 1 to the pass gate 120 of each cell 110 in the first subset for a first duration, wherein the first subset of cells comprises all cells suffering a write 0 failure and the first array supply voltage is greater than an operational array supply voltage of the cell. In one embodiment, the first array supply voltage may be from about 1.1 times the operational array supply voltage to about 1.8 times the operational array supply voltage. Independently of the first array supply voltage, the first duration may be from about 1 sec to about 10 sec.

FIG. 7 depicts a timing diagram that may be used in performing the applying (at 630) the first array supply voltage. In the depicted timing diagram, all signals expect the WL signals and VCS may be controlled by a tester device/operator. The depicted set of signals may be particularly useful for stressing the PUR 132R and PDL 134L transistors of cell 110 depicted in FIG. 2. A reversed set of signals may be useful to apply a comparable array supply voltage to the PUL 132L and PDR 134R transistors of cell 110 depicted in FIG. 2.

FIG. 8 depicts a flowchart showing one embodiment of the applying (at 630) in more detail. First, at 810, a self-time mode is disabled. Next, at 815, solid write x is run, where x has a value opposite to the type of write failure in question. For example, if the number of write failures in a word line for write 0 is greater than the first threshold, a solid write 1 may be run. If the number of write failures in a word line for write 1 is greater than the first threshold, a solid write 0 may be run.

At 820, CK is kept High and BISHW is set High for the stress time TSTR. The value of TSTR may be calculated based on one or more of the desired incremental Vt shift in the array 105, the stress voltage VSTR to be applied, and the available BTI models (i.e., PBTI or NBTI). In this embodiment, only the first subset of word lines, i.e., those with a number of write failures greater than the first threshold will experience the stress voltage for the stress time.

Cells which are not members of the first subset may be screened from experiencing the stress voltage by the action of a row decoder (not shown). Alternatively or in addition, cells which are not members of the first subset may be screened from experiencing the stress voltage by undergoing a regimen of 50% write 1, 50% write 0 during the stress time for the first subset of cells.

At 830, BISHW and CK are both set Low, and a determination is made at 840 whether all failing rows, i.e., all word lines comprising cells in the first subset, have been stressed. If so, applying (at 630) may end (block 860). If no, flow then returns to 810, and applying at 630 continues until end block 860 is reached.

Thereafter, flow of the method 600 may proceed to applying (at 640) a second array supply voltage to the latch of each cell in a second subset of the cells and a write 0 to the pass gate of each cell in the second subset for a second duration, wherein the second subset of cells comprises all cells suffering a write 1 failure and the second array supply voltage is greater than an operational array supply voltage of the cell. The values of the second array supply voltage, the second duration, etc. may be selected according to the descriptions of the first array supply voltage, first duration, etc. referred to above with reference to applying at 630. Particularly, the logic and/or techniques for screening cells from unneeded stress may be as described above.

In one embodiment, the method 600 may further comprise applying (at 650) a write 0 to the pass gate of each cell in a third subset of cells for 50% of a third duration, and a write 1 to the pass gate of each cell in the third subset for 50% of the third duration, wherein the third subset comprises all cells not identified as suffering a write 0 failure and not identified as suffering a write 1 failure.

In one embodiment, each of the cells may be a static random access memory (SRAM) cell. In a particular embodiment, each of the SRAM cells may be a six-transistor (6T) SRAM cell.

The method 600 may be performed during semiconductor device manufacturing, such as that depicted in FIG. 7. Alternatively or in addition, a semiconductor device 100 may be configured to perform the method 600 on arrays 105 contained within or in the same system as the semiconductor device 100 at one or more times during the operational life of the semiconductor device 100. For example, if the cells 110 are SRAM cells, if the semiconductor device 100 performs the method 600 during its operational life, the stability and/or yield of the SRAM cells may be maintained at a desirably high level for a longer time than would otherwise be possible.

The methods described above may be governed by instructions that are stored in a non-transitory computer readable storage medium and that are executed by, e.g., a processor in a computing device. Each of the operations described herein (e.g., FIG. 6) may correspond to instructions stored in a non-transitory computer memory or computer readable storage medium. In various embodiments, the non-transitory computer readable storage medium includes a magnetic or optical disk storage device, solid state storage devices such as flash memory, or other non-volatile memory device or devices. The computer readable instructions stored on the non-transitory computer readable storage medium may be in source code, assembly language code, object code, or other instruction format that is interpreted and/or executable by one or more processors.

The particular embodiments disclosed above are illustrative only, as the invention may be modified and practiced in different but equivalent manners apparent to those skilled in the art having the benefit of the teachings herein. For example, the disclosure may be applied to a variety of circuit elements in addition to the 6T SRAM cells described and depicted in particular embodiments of the description and figures. For another example, the process steps set forth above may be performed in a different order. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is, therefore, evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below. 

What is claimed is:
 1. A method, comprising: identifying each cell suffering a write 0 failure in an array comprising a plurality of cells, wherein each of the cells comprises a pass gate and a latch; identifying each cell suffering a write 1 failure in the array; applying a first array supply voltage to the latch of each cell in a first subset of the cells and a write 1 to the pass gate of each cell in the first subset for a first duration, wherein the first subset of cells comprises all cells suffering a write 0 failure and the first array supply voltage is greater than an operational array supply voltage of the cell; and applying a second array supply voltage to the latch of each cell in a second subset of the cells and a write 0 to the pass gate of each cell in the second subset for a second duration, wherein the second subset of cells comprises all cells suffering a write 1 failure and the second array supply voltage is greater than an operational array supply voltage of the cell.
 2. The method of claim 1, wherein the first threshold is zero and the second threshold is zero.
 3. The method of claim 1, wherein each of the cells is a static random access memory (SRAM) cell.
 4. The method of claim 3, wherein each of the SRAM cells is a six-transistor (6T) SRAM cell.
 5. The method of claim 1, wherein the first array supply voltage is from about 1.1 times the operational array supply voltage to about 1.8 times the operational array supply voltage; the second array supply voltage is from about 1.1 times the operational array supply voltage to about 1.8 times the operational array supply voltage; the first duration is from about 1 sec to about 10 sec, and the second duration is from about 1 sec to about 10 sec.
 6. The method of claim 1, further comprising applying a write 0 to the pass gate of each cell in a third subset of cells for 50% of a third duration, and a write 1 to the pass gate of each cell in the third subset for 50% of the third duration, wherein the third subset comprises all cells not identified as suffering a write 0 failure and not identified as suffering a write 1 failure.
 7. A semiconductor device, comprising: a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage.
 8. The semiconductor device of claim 7, wherein the first number of cells is two, four, six, eight, sixteen, thirty-two, or sixty-four.
 9. The semiconductor device of claim 7, wherein each cell is a static random access memory (SRAM) cell.
 10. The semiconductor device of claim 9, wherein each of the SRAM cells is a six-transistor (6T) SRAM cell.
 11. The semiconductor device of claim 7, wherein the first array supply voltage is from about 1.1 times the operational array supply voltage to about 1.8 times the operational array supply voltage and the second array supply voltage is from about 1.1 times the operational array supply voltage to about 1.8 times the operational array supply voltage.
 12. A system, comprising: a semiconductor device, comprising: a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; an array VCS driver electrically connected to each VCS; and a control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage; and a test and repair controller configured to: identify each cell suffering a write 0 failure in an array comprising a plurality of cells, wherein each of the cells comprises a pass gate and a latch; identify each cell suffering a write 1 failure in the array; apply a first array supply voltage to the latch of each cell in a first subset of the cells and a write 1 to the pass gate of each cell in the first subset for a first duration, wherein the first subset of cells comprises all cells suffering a write 0 failure and the first array supply voltage is greater than an operational array supply voltage of the cell; and apply a second array supply voltage to the latch of each cell in a second subset of the cells and a write 0 to the pass gate of each cell in the second subset for a second duration, wherein the second subset of cells comprises all cells suffering a write 1 failure and the second array supply voltage is greater than an operational array supply voltage of the cell.
 13. The system of claim 12, wherein the first number of cells is two, four, six, eight, sixteen, thirty-two, or sixty-four.
 14. The system of claim 12, wherein each cell is a static random access memory (SRAM) cell.
 15. The system of claim 14, wherein each of the SRAM cells is a six-transistor (6T) SRAM cell.
 16. The system of claim 12, wherein the first threshold is zero and the second threshold is zero.
 17. The system of claim 12, wherein the first array supply voltage is from about 1.1 times the operational array supply voltage to about 1.8 times the operational array supply voltage and the second array supply voltage is from about 1.1 times the operational array supply voltage to about 1.8 times the operational array supply voltage.
 18. The system of claim 12, wherein the first duration is from about 1 sec to about 10 sec.
 19. The system of claim 12, further comprising applying a write 0 to the pass gate of each cell in a third subset of cells for 50% of a third duration, and a write 1 to the pass gate of each cell in the third subset for 50% of the third duration, wherein the third subset comprises all cells not identified as suffering a write 0 failure and not identified as suffering a write 1 failure.
 20. The system of claim 12, further comprising: a process controller, configured to provide an instruction set for manufacture of the semiconductor device to a manufacturing system; the manufacturing system, configured to manufacture the semiconductor device according to the instruction set, wherein the instruction set comprises instructions to: form the plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; form the plurality of word lines, wherein each word line comprises a supply voltage line (VCS) which supplies voltage to each latch of a first number of cells; form the array VCS driver electrically connected to each VCS; and form the control line configured to provide an operational array supply voltage, a first array supply voltage, or a second array supply voltage to each VCS, wherein the first array supply voltage and the second array supply voltage are greater than the operational array supply voltage. 